TAKAGI & TAKENAKA Laboratory Group

Ge MOSFET

High-mobility Ge is one of the most promising channel materials for future deeply-scalded MOSFETs.

A high quality Ge MOS interface is a key issue for the Ge MOSFETs. We have recently found GeO2/Ge interface formed by thermal oxidation at high temperature exhibited the lowest interface state density among a variety of Ge MOS interfaces [1]. We have evaluated the MOS interface properties by the low temperature conductance method, and the interface state density of less than 10¹¹ cm^-2 eV^-1 was obtained. The GeO2/Ge p-MOSFET was also demonstrated with the 3x higher hole mobility than Si [2]. We have also successfully demonstrated high performance Ge n-MOSFETs with n+S/D formed by the gas phase doping [3]. We have also investigated ECR plasma post oxidation after for EOT scaling of the Ge MOS gate stack. The high-quality Ge MOS interface with EOT of 0.76 nm has been successfully demonstrated by the post plasma oxidation. The high-performance Ge CMOS with EOT of 0.76 nm have also been successfully demonstrated [4-7].

The Ge condensation and wafer bonding technique has also been investigated for forming Ge-on-Insulator (GOI) and SiGe-on-Insulator (SGOI) integrated on Si wafers [8-10]. (100) and (110) GOI MOSFETs were successfully demonstrated.

By using the direct wafer bonding, the III-V/Ge CMOS structure was demonstrated for the first time [11].

TEM image of GeO2/Ge MOS interface

Output characteristics of Ge CMOS formed by plasma post oxidation

Ge condensation by thermal oxidation

III-V/Ge CMOS

III-V MOSFET

III-V semiconductors have attracted attention as candidates of high performance n-MOSFETs because of their high intrinsic electron mobilities and low effective masses.

In order to integrate the III-V materials with the conventional Si platform, we are conducting the research on the direct wafer bonding technology[1-2]. The III-V-on-Insulator (III-V-OI) on Si wafer has been successfully obtained by bonding an InGaAs/InP wafer to an SiO2/Si wafer. We have obtained extremely-thin-body 3-nm-thick InGaAs layer on Si by wafer bonding and well-behaved MOSFET operation [3].

Metal S/D technology has also been investigated, which enables self-align low-resistance S/D with low temperature instead of conventional ion implantation [4-5]. We have found that Ni-InGaAs alloy can be obtained by direct reaction of Ni and InGaAs, which suitable for self-align metal S/D for InGaAs MOSFETs. We have successfully demonstrated deeply-scaled metal S/D InGaAs MOSFETs with 55-nm gate length fabricated on III-V-OI on Si wafer [6].The 20-nm-gate-length InGaAs FINFET has also been demonstrated [7].

InGaAs MOS interface has also been investigated by using atomic layer deposition (ALD). We found that the HfO2/InGaAs MOS interface properties was strongly dependent on the deposition temperature of HfO2. The HfO2/InGaAs MOS interface with 200 ℃ deposition exhibited lowest interface trap density[7]. We have also found that interfacial layer of 2-cycle Al2O3 between HfO2 and InGaAs improved the interface properties, and MOS interface with CET of 1.08 nm has been successfully demonstrated[8]. The interface traps inside the conduction band of InGaAs have also been investigated. We have clarified that the interface traps inside the conduction band affected the transistor performances by using Hall measurements and C-V measurements[9].

III-V-on-insulator wafer bonded on Si

Self-align Ni-InGaAs metal S/D for Ni-InGaAs MOSFETs

TEM image and C-V characteristic of HfO2/Al2O3/InGaAs MOS capacitor with CET of 1.08 nm

Tunnel FET

It is well known that the theoretical lower limit of S.S. in MOSFETs amounts to 60 mV/dec at room temperature because of the nature of the operation principle of MOSFET This fact leads to an essential limitation of scaled CMOS under future technology nodes especially in terms of driving voltage scaling. Thus, tunneling field-effect transistors (TFETs) have recently stirred a strong interest as one candidate of promising low power switching devices with S.S. lower than 60 mV/dec at room temperature.

We have investigated InGaAs-based tunnel FETs because the higher unneling probability associated with the lower tunneling barrier, the smaller tunneling mass and the direct tunneling properties in InGaAs as compared with Si.
We have successfully demonstrated lateral-pin-structure InGaAs tunnel FETs.
We are currently trying to improve the transistor characteristics of InGaAs tunnel FETs.

Operation principle of Tunnel FET

InGaAs tunnel FET

Ge/Si tunnel FET

On-chip optical interconnect

The performance of MOSFETs in large-scale integrated circuit (LSI) have been enhanced by the scaling law. However, the power consumption and signal delay in interconnect of LSI has been serious issues, which cannot be resoved by device scaling. To resove the interconnect issues, we have investigated on-chip optical interconnect using Si photonics. Si photonics is the standard platform for large-scale photonic integrated circuits (PICs). We have investigaed the heterogeneous integration of SiGe, Ge, and III-V semiconductors on Si photonics platform for on-chip and off-chip optical interconnects.

Strained SiGe optical modulator

Si optical modulators are one of the fundamental building for optical interconnections, however the modulation efficiency of Si modulators is poor due to the weak plasma dispersion effect in Si. To overcome this problem, we have proposed to enhanced the free carrier effects by introducing a light-effectice-mass semiconductor on Si photonics platform [1]. We have investigated Si optical modulators with strained SiGe which has a light hole effective mass due to the compressive strain. Owing to the light hole effective mass, we have predicted that strained SiGe exhibits larger plasma dispersion effect than Si [1]. By using carrier-injection SiGe optical modulator, we have successfully demonstrated the enhanced plasma dispersion effect and free-carrier absorption [2-4]. We have also demonstrated 10 Gbps modulation in the Mach-Zehnder interferometer SiGe optical modulator [5]. Since SiGe has been widely used in CMOS fabs, we are now investigating with companies to make real products [6].

Strained SiGe optical modualtor

III-V/Si hybrid MOS optical modulator

Since III-V semiconductors have a light electron effectice mass, the electron-induced refractived index change in III-V semiconductors such as InGaAsP is expected to be significantly greater than that in Si. Thus, we have proposed III-V/Si hybrid MOS optical modulator by bonding an n-InGaAsP layer on a Si waveguide with a thin Al2O3 gate dielectric [1-4]. We have successfully achieved optical phase modulation by using accummulated electrons at the InGaAsP MOS interface for the first time. We have achieved an extreamly high modualtion efficiency of 0.047 Vcm, which is one of the highest modulation efficiency among semiconductor-based optical modulators reporeted so far. The optical loss accompanied with optical phase modulation is also reduced by 1/10, enabling high-efficiency, low-loss, and high-speed optical modulators. Now, we are conducting the research of Si optical modualtors beyond 100 Gbps modulation speed.

III-V/Si hybrid MOS optical modulator

Ge photodetector

High-sensitivity Ge photodetectors (PDs) has been investigated. One of the critical issues of Ge PDs is large dark current as compared with InGaAs PDs. We have successfully reduced the dark current of the Ge PDs by forming n+/p junction by gas-phase doping [1] instead of ion implantation. In addition, it was found that the GeO2 surface passivation was effective to reduce the surface leakage current[2, 3]. We have also successfully fabricated Ge-on-Insulator wafers by using direct wafer bonding. On the GeOI wafer, we have successfuly demonstrated a waveguide Ge PD monolithically integrated with a-Si passive waveguides [4]. We are now investigating the Ge/a-Si hybrid platform which can integrated Ge/GeSn lasers, Ge modulators, Ge PDs, and a-Si passive waveguides on the GeOI wafer.

Ultra-low dark current Ge PD

Ge/a-Si hybird platform

III-V CMOS photonics

We have proposed the III-V CMOS photonics platform on which ultra-small III-V photonics and high-performance III-V transistors can be monolithically integrated [1, 2]. By using III-V-on-Insulator (III-V-O) wafers, which is similar to silicon-on-Insulator (SOI) wafers for Si photonics, we can achieve the strong optical confinement in the III-V-OI, enabling ultra-small III-V photonic devices. The SOI-based waveguide itself does not allow active functionalities, while InP-based photonic wire can achieve active/passive integration, much suitable for ultimately high-performance electronic-photonic integrated circuits (EPIC). We are investigating Si-photonics-like III-V photonics by using the III-V CMOS photonics platform. We have successfully fabricated the III-V-OI wafer on Si by the direct wafer bonding of an InGaAsP/InP wafer and an SiO2/Si wafer [3]. By using the III-V-OI wafer, we have successfully demonstrated an ultra-small bend waveguide, an ultra-small arrayed waveguide grating [3], a grating coupler [4]. We have also demonsrated active devices such as a carrier-injection modulator/switch [4, 5] and waveguide InGaAs PD [6-8]. Moreover, we have successfully achieved monolithic integration of an InGaAsP optical modualtorand an InGaAsP driver MOSFET. Now we are conducting the research for electronic-photonic integrated circuits (EPICs) which can integrate lasers, modualtors, photodetectors, and InGaAs MOSFET on the III-V CMOS photonics platform based on CMOS technologies.

III-V CMOS photonics platform

Active and passive devices on III-V CMOS photonics platform

Deep learning based on universal photonic integrated circuits

Owing to the recent development of Si photonic technolgies, universal photonic integrated circuits (PICs) composed of meshed Mazh-Zehnder interferometer switches have gain considerable attention. Universal PICs are able to perform arbitrary linear operations, enabling various functionalties for optical communications, LiDAR, deep learning based on photonic neural network, and quantum computing. It is essential for universal PICs to realize high-peformance optical phase shifter on Si PICs. We have successfully demonstrated a Si hybrid MOS optical phase shifter, exhibting 1000 times faster switching speed and 1 million smaller power cosumption than a thermo-optic optical phase shifter [1, 2]. By using a Si hybrid MOS optical phase shifter, we can enhance the performance of a universal PIC significantly. We have conducted research of deep learning using universal PICs with Si hybrid MOS optical phase shifter [3].

Deep learning using universal photonic integrated circuits with III-V/Si hybrid MOS optical phase shifters

MIR photonic integrated circuits

Recently mid-infrared (MIR) photonic integrated circuits (PICs) has gain considerable attention for fiber/free-space optical communication and optical sensing applications. Since many molecules have strong optical absorption in MIR wavelengths from 2 um to 15 um associated with molecular vibrations, MIR photonics is particularly promising for bio-medical sensors, gas sensors, and environmental monitors. Compared to near infrared light for optical fiber communication, MIR light has not been fully utilized because of the technology issues. However, the recent development of Si photonics enables Si MIR PICs. Due to the absorption of Si, Si MIR PICs cannot operation beyond 7 um wavelenth. To overcome this problem, we have investigated Ge-based MIR PICs which can operation at the entire MIR spectrum. We have proposed the Ge CMOS photonics platform which can integrate Ge MIR waveguides and Ge CMOS on Ge-on-Insulator (GeOI) wafer [1-4]. We have successfully fabricated high-quality GeOI wafer using wafer bonding. Thus, various Ge passive waveguides such as micro bends, MMI couplers, ring resonators, grating couplers, photonic crystal cavities have been demonstrated on the GeOI wafer. We have also demonsrated carrier-injection Ge optical modulator operation at MIR wavelength for the first time. Now we are exploring the new frontier of Ge MIR PICs for sensing and optical communication.

Ge CMOS photonics platform

Ge active and passive devices

2D material devices

After the successful exfoliation of single-layer graphene, 2D materials have been intensively investigated around the world because of thier unique material properties. By using metal-like graphene, semiconducting TMDs such MoS2, and insulating h-BN, various electronic and photonic devices and flexible integrated ciruits have been investigated. We are conducing graphene modulator/photodetector [1, 2] and MoS2 MOSFETs [3].

2D materials

Graphene based photonic devices and MoS2 MOSFET