TAKAGI & TAKENAKA Laboratory Group

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Welcome to TAKAGI and TAKENAKA Laboratory Group!
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Heterogeneous integration for low-power electronics and Si/III-V CMOS photonics

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The performance of Si LSIs has been enhanced over 30 years by increasing the number of transistors with the Moore's law. The transistor number of the latest CPU is already over 1 billion. As is well known, the scaling rule of the Si transistor has made it possible to enhance the performance of the LSIs. The gate length has already been scaled down to less than 30 nm, and the technology roadmap expects further scaling. However, the miniaturization of the transistors becomes increasingly difficult due to the physical limitations, and the conventional scaling rule will not be enough to enhance the performance of the LSIs. Therefore, some breakthrough technologies are strongly required for the Si LSI in order to enhance the device performance even in the post-scaling era.

The Takagi-Takenaka group researches the post-scaling semiconductor devices for low-power LSI and on-chip optical interconnection.

The research topics are as below.

  • Ge/III-V MOSFETs
  • Tunnel FETs
  • Si photonics
  • III-V CMOS photonics
  • Graphene photonics
  • 2D material electronics

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